So I made a choice.
First, I decide to remove any reference of MZ-800 from the source: unlike MZ-1500 which still shares a lot of similiraty with MZ-700 in hardware - especially they have both the same LSI - MZ-800 is a complete different beast when not in mz-700 mode and the LSI is totally different.
Second, I added some partial T-states tables to count accumulated T-states by memory access steps (up to 6 for an instruction, including opcode fetchings). For instance, if I have a cc_op table for main instructions I have a mc_op table as follows:
Code: Select all
static const uint8_t cc_op[0x100] = {
4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11,
5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11
};
// Memory cycles: [fMfetch][fMread/write]*
static const uint8_t mc_op[0x100][6] = {
// x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
{4 },{4,7,10},{4,7 },{6 },{4 },{4 },{4,7 },{4 },{4 },{4 },{4,7 },{6 },{4 },{4 },{4,7},{4 }, // 0x
{5,8 },{4,7,10},{4,7 },{6 },{4 },{4 },{4,7 },{4 },{4,7 },{4 },{4,7 },{6 },{4 },{4 },{4,7},{4 }, // 1x
{4,7 },{4,7,10},{4,7,10,13,16},{6 },{4 },{4 },{4,7 },{4 },{4,7 },{4 },{4,7,10,13,16},{6 },{4 },{4 },{4,7},{4 }, // 2x
{4 },{4,7,10},{4,7,10,13 },{6 },{4,8,11 },{4,8,11},{4,7,10},{4 },{4,7 },{4 },{4,7,10,13 },{6 },{4 },{4 },{4,7},{4 }, // 3x
{4 },{4 },{4 },{4 },{4 },{4 },{4,7 },{4 },{4 },{4 },{4 },{4 },{4 },{4 },{4,7},{4 }, // 4x
{4 },{4 },{4 },{4 },{4 },{4 },{4,7 },{4 },{4 },{4 },{4 },{4 },{4 },{4 },{4,7},{4 }, // 5x
{4 },{4 },{4 },{4 },{4 },{4 },{4,7 },{4 },{4 },{4 },{4 },{4 },{4 },{4 },{4,7},{4 }, // 6x
{4,7 },{4,7 },{4,7 },{4,7 },{4,7 },{4,7 },{4 },{4,7 },{4 },{4 },{4 },{4 },{4 },{4 },{4,7},{4 }, // 7x
{4 },{4 },{4 },{4 },{4 },{4 },{4,7 },{4 },{4 },{4 },{4 },{4 },{4 },{4 },{4,7},{4 }, // 8x
{4 },{4 },{4 },{4 },{4 },{4 },{4,7 },{4 },{4 },{4 },{4 },{4 },{4 },{4 },{4,7},{4 }, // 9x
{4 },{4 },{4 },{4 },{4 },{4 },{4,7 },{4 },{4 },{4 },{4 },{4 },{4 },{4 },{4,7},{4 }, // Ax
{4 },{4 },{4 },{4 },{4 },{4 },{4,7 },{4 },{4 },{4 },{4 },{4 },{4 },{4 },{4,7},{4 }, // Bx
{5,8,11},{4,7,10},{4,7,10 },{4,7,11 },{4,7,11,14,17},{5,8,11},{4,7 },{5,8,11,14,17},{5,8,11},{4,7,10},{4,7,10 },{4 },{4,7,11,14,17},{4,7,11,14,17},{4,7},{5,8,11,14,17}, // Cx
{5,8,11},{4,7,10},{4,7,10 },{4,7 },{4,7,11,14,17},{5,8,11},{4,7 },{5,8,11,14,17},{5,8,11},{4 },{4,7,10 },{4,7},{4,7,11,14,17},{4 },{4,7},{5,8,11,14,17}, // Dx
{5,8,11},{4,7,10},{4,7,10 },{4,7,11,14},{4,7,11,14,17},{5,8,11},{4,7 },{5,8,11,14,17},{5,8,11},{4 },{4,7,10 },{4 },{4,7,11,14,17},{4 },{4,7},{5,8,11,14,17}, // Ex
{5,8,11},{4,7,10},{4,7,10 },{4 },{4,7,11,14,17},{5,8,11},{4,7 },{5,8,11,14,17},{5,8,11},{6 },{4,7,10 },{4 },{4,7,11,14,17},{4 },{4,7},{5,8,11,14,17} // Fx
};
Consider "<----" marks for the additions.
And so on. I still need to finish the mc tables for the hellish xy and ixcb (IX/IY relative opcodes).
The VRAM interception with the "right" t-states is now handled with such cases as:
I don't think it is perfect because the emulator will read/write BEFORE waiting the necessary cycles while the genuine MZ-700 will do so AFTERWARD.
Note: The case of an instruction starting with BLANK=1 then ending with BLANK=0 may not be handled fine here.