Jo Even wrote: ↑Thu Jun 20, 2019 8:43 pm
Would it be possible to create a VBL interrupt too?
I see major issues:
1) there is only one /INT signal (regardless /NMI) and it is used for timer2.
2) CPU runs in IM1 mode (RST 38h).
While using /EXINT would certainly allow to raise an interrupt, it would call the same routine and so you need to alter the monitor code so it can distinguish the source.
/VBLK is issued by the ASIC and it is not clear if it is set in high-impedence when not asserted negatively. Why the question? well if you want to have several controllers be able to use /EXINT, I think it's pretty clear that they may all be high-impedance when not asserted negatively so they cannot affect the others if they output a high signal instead.
While using IM2 would allow using a vector table (I * 256 + DBUS[0..7]), it means every controller should provide an vector offset on the data bus when raising an interrupt (it also means each controller should synchronize to avoid outputting the data bus at the same time).
So in the end, we need an interrupt controller which is the only one to use /EXINT preferably. We keep IM1 because of timer2 which doesn't provide an offset. When calling RST 38h, the routine first check by reading a status port of the interrupt controller to determine the interrupt source. If no source, timer1. To be honest, even this way is not great: you can still receive /INT1 (timer2) AND /EXINT in the same time and still be unable to detect whether /INT1 raises.
The best approach would be to deroute /INT1 as one of the sources for the interrupt controller but it would means some changes on the motherboard and in the monitor code.
Or we keep /INT1 as such (/INT1 and /EXINT are ANDed) but we also provide /INT1 as a source to the interrupt controller which will also assert negatively /EXINT so the interrupt routine can retrieve that /INT1 is also asserted negatively. There could be some timing issue between /INT1 and the resulted /EXINT though... or not.