[MZ-700] Vsync Checker

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hlide
Posts: 484
Joined: Thu Jan 25, 2018 9:31 pm

[MZ-700] Vsync Checker

Post by hlide »

Add a new project on GitHub/SHARPENTIERS: MZ-700-VsyncChecker.
Try to determine how many BLNK signals the program can count in a frame through PIT counters #1 and #2.
hlide
Posts: 484
Joined: Thu Jan 25, 2018 9:31 pm

Re: [MZ-700] Vsync Checker

Post by hlide »

Results:

- Genuine MZ-700 tells me: 306 - 106 = 200. Timer #2 only counts ~306 BLNKs in a frame?

- EmuZ-700/PAL tells me: 308 - 108 = 200. Timer #2 only counts ~308 BLNKs in a frame?

My logic analyzer tells me there is 312 BLNK signals per frame. So how does it happen the timer #2 is missing 6 BLNKs?
VsyncChecker.jpg
hlide
Posts: 484
Joined: Thu Jan 25, 2018 9:31 pm

Re: [MZ-700] Vsync Checker

Post by hlide »

More precisely, the logic analyzer tells me: 312 - 112 = 200.
VsyncChecker.jpg
because the timers #2 is indeed counting two BLNK pulses as unit, I can imagine missing one unit but that would be 310. Here, we're missing 3 units.
hlide
Posts: 484
Joined: Thu Jan 25, 2018 9:31 pm

Re: [MZ-700] Vsync Checker

Post by hlide »

So the Intel 8253 document says the counter decreases from N to 1 at raising edge of CLK (BLNK=1) and if 0, set OUT to 0 at falling edge of CLK then to 1 at raising edge of CLK. When the counter decreases to 0 the next value will be N-1.

What seems to happen is the initial count is N+1 when N written to the counter, then subsequent N when wrapping. So the BLNK counting for timer #1 decrements at 4th BLNK and then BLNK counting for timer #2 decrements at 2 BLNKs later. So the counting starts at 6th BLNK. That may explain why the genuine MZ-700 is giving 306 (312 - 6).

EmuZ-700 is not emulating timer #1 as it should be (it sets its frequency at fCPU / 228) instead of connecting the OUT1 of timer #1 to CLK2 of timer #2. Not sure how to make it more compatible though...

Code: Select all

___/WR________________________________________________________________________________________________________________________________________________________
   \_/ 2      : 1st BLNK                 2nd BLNK |               3rd BLNK                 4th BLNK |               5th BLNK                 6th BLNK |
BLNK (CLK1)    __________               __________|              __________               __________|              __________               __________|
\_____________/    2     \_____________/    1     \_____________/    0     \_____________/    1     \_____________/    0     \_____________/    1     \_______
                                                  |                                                 |                                                 |
OUT1______________________________________________|                         ________________________|                         ________________________|
CLK2                                              \________________________/           1            \________________________/           0            \______
1st decrease for timer #1 (MODE 2) -----------------------------------------------------------------^ here !                                          |
                                                                                                                                                      |
OUT2__________________________________________________________________________________________________________________________________________________|
                                                                                                                                                      \______            
1st decrease for timer #2 (MODE 0)--------------------------------------------------------------------------------------------------------------------^ here !
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